Non-volatile computing method in flash memory

ABSTRACT

An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash array, storing weight values W i,n . A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. Bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values X i,n  on the corresponding inputs. Current sensing circuits are connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents.

BACKGROUND Field

The present invention relates to circuitry that can be used to perform in-memory computation, such as multiply and accumulate or other sum-of-products like operations.

Description of Related Art

In neuromorphic computing systems, machine learning systems and circuitry used for some types of computations based on linear algebra, the multiply and accumulate or sum-of-products functions can be an important component. Such functions can be expressed as follows:

${f\left( X_{i} \right)} = {\sum\limits_{i = 1}^{M}{W_{i}X_{i}}}$

In this expression, each product term is a product of a variable input X_(i) and a weight W_(i). The weight W_(i) can vary among the terms, corresponding for example to coefficients of the variable inputs X_(i).

The sum-of-products function can be realized as a circuit operation using cross-point array architectures in which the electrical characteristics of cells of the array effectuate the function. One problem associated with large computations of this type arises because of the complexity of the data flow among memory locations used in the computations which can involve large tensors of input variables and large numbers of weights.

It is desirable to provide structures for sum-of-products operations suitable for implementation in-memory, to reduce the number of data movement operations required.

SUMMARY

A technology for in-memory multiply and accumulate functions is described. In one aspect, the technology provides a method using an array of memory cells, such as NOR flash architecture memory cells.

One method described includes programming M memory cells in a row of the array on a particular word line WLn, and on a plurality of bit lines BLi, for i going from 0 to M−1, with values W_(i,n), for i going from 0 to M−1, or accessing already programmed memory cells by for example controlling a row decoder to select a word line for a particular row of programmed cells. The values W_(i,n), can correspond with weights, or coefficients, of the terms in a sum-of-products or multiply and accumulate function that uses the cells on word line WLn, and bit line BLi. The values W_(i,n) can be based on multiple bits per cell. In NOR flash memory embodiments, the values W_(i,n) correspond with threshold values of the memory cells. Also, this method includes biasing the bit lines BLi, with input values X_(i,n), respectively, for i going from 0 to M−1 for the cells on the word line WLn. The input values can be analog bias voltages that are generated using a digital-to-analog converter in response to multibit digital input signals for each term of the sum-of-products function. This method includes applying a word line voltage to the particular word line WLn so that the memory cells on the row conduct current corresponding to a product W_(i,n)*X_(i,n) from respective cells in the row. The currents conducted by the cells in the row represent respective terms of a sum-of-products function, and are summed to produce an output current representing a sum of the terms. The output current is sensed to provide the result of the in-memory computation of the sum-of-products function.

In some embodiments, the row of memory cells in an array can be configured into P sets of M cells each, and M is greater than 1. The output current from each of the P sets of M cells can be summed in parallel.

In some embodiments, multiple rows of the array can be programmed or accessed, and results computed for each row in sequence according to control circuitry and commands applied to configure the operation. Also, in some embodiments, multiple rows of the array can be programmed or accessed in a single sensing operation, and results computed for each bit line according to control circuitry and commands applied to configure the operation.

Also, an in-memory multiply and accumulate circuit is described. In an example described herein, the circuit includes a memory array including memory cells on a set of word lines and a set of bit lines, such as a NOR flash array, storing respective weight values W_(i,n). A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. A plurality of bit line bias circuits is included. Bit line bias circuits have corresponding inputs connected to an input data path, and have outputs connected to respective bit lines in the set of bit lines. The bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values X_(i,n) on the corresponding inputs. A circuit includes a plurality of current sensing circuits, each of the plurality of current sensing circuits is connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents from the corresponding multi-member subset of bit lines. In some embodiments, the multimember subset of bit lines can be the entire set of bit lines. In other embodiments, the circuit can include a plurality of multimember subsets usable in parallel.

In other embodiments, a row decoder is coupled to the set of word lines, and configured to apply word line voltages to select a plurality of word lines in the set to access a plurality of memory cells in parallel. A plurality of bit line bias circuits is included. Bit line bias circuits have corresponding inputs connected to an input data path, and have outputs connected to respective bit lines in the set of bit lines. The bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values X_(i,n) on the corresponding inputs. A circuit includes a plurality of current sensing circuits, each of the plurality of current sensing circuits is connected directly or via a switch, to receive current from a selected one of the bit lines, and to produce an output in response to a sum of currents from the corresponding plurality of memory cells on the selected bit line.

In some embodiments, the bit line bias circuits can comprise digital-to-analog DAC converters.

Also, in one circuit described herein, some or all of the memory cells in the array are connected between corresponding bit lines and a common reference line, which can be referred to in connection with a NOR flash array as a common source line. A source line bias circuit can be connected to the common source line, and to the bit line bias circuits to compensate for variations in the voltage on the common source line.

Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of an in-memory sum-of-products circuit according to embodiments described herein.

FIG. 2 is a simplified diagram of an alternative implementation of an in-memory sum-of-products circuit according to embodiments described herein.

FIG. 3 is a more detailed diagram of a sum-of-products circuit according to embodiments described herein.

FIG. 4 is a graph showing distributions of threshold voltages which correspond to weights or coefficients stored in memory cells in embodiments described herein.

FIG. 5 is a diagram of an example digital-to-analog converter usable as a bit line bias circuit in embodiments described herein.

FIG. 6 is a diagram of an example sense amplifier suitable for sensing current sums according to embodiments described herein.

FIG. 7 is a timing diagram showing operation of the sense amplifier of FIG. 6.

FIG. 8 is a logic table showing operation of the sense amplifier of FIG. 6.

FIG. 9 is a flowchart of an in-memory sum-of-products operation according to embodiments described herein.

FIG. 10 is a more detailed diagram of an alternative sum-of-products circuit according to embodiments described herein.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to the FIGS. 1-10.

FIG. 1 illustrates an in-memory sum-of-products circuit. The circuit includes an array 10 of NOR flash cells. The array 10 includes a plurality of bit lines BL0 and BL1 and a plurality of word lines WL0 and WL1.

Memory cells in the array are disposed on the plurality of bit lines and the plurality of word lines. Each memory cell stores a weight W_(0,0); W_(1,0); W_(0,1); W_(1,1); which acts as a coefficient of a term of the sum-of-products function.

Word line circuits 11, which can include word line decoders and drivers are configured to apply word line voltages on selected word lines in support of the sum-of-products function.

Bit line circuits 12 include circuitry to bias each bit line in the plurality of bit lines with a bias voltage that corresponds to an input value for each term of the sum-of-products function, where inputs X_(0,n) and X_(1,n) correspond with the input value for bit line BL0 and bit line BL1 stored in cells on a particular word line WLn.

The outputs from the bit line circuits for bit lines BL0 and BL1 represented in FIG. 1 as I-cell 1 and I_cell 2 are coupled to a summing node 13 to produce an output current ISENSE for the plurality of cells. The output current ISENSE is connected to a sense amplifier 14 which outputs a value corresponding to the sum of the terms W_(0,n)*X_(0,n)+W_(1,n)*X_(1,n).

Control circuits 15 are configured to execute operations to program the weights in the cells in the array, and to execute the sum-of-products operations. The programming can be implemented using state machines and logic circuits adapted for programming the particular type of memory cell in the array. In embodiments described herein, multibit programming, or multilevel programming, is utilized to store weights that can have 2-bit, 3-bit, 4-bit or more bit values or effectively an analog value. In support of programming, circuitry such as a page buffer, program voltage generators, and program pulse and verify sequence logic can be included.

The control circuits 15 in support of executing sum-of-products operations, can include a sequencer or decoder that selects word lines corresponding to the rows of weights to be used in a particular cycle of calculation. In one example, a sequence of computations can be executed by applying word line voltages to the word lines in the array in sequence to access corresponding rows of cells, while input values corresponding to each row are applied in parallel for each sequence on the bit line circuits. The sum of products computation can comprise a sum of currents in one or more selected memory cells on a plurality of bit lines, or in other embodiments, a sum of currents in a plurality of memory cells on one bit line.

The control circuits 15 can also include logic for controlling the timing and functioning of the sense amplifier 14, for generating multibit outputs in response to the output current ISENSE.

In the example illustrated by FIG. 1, the memory cells in the array can include charge storage memory cells, such as floating gate cells or dielectric charge trapping cells, having drain terminals coupled to corresponding bit lines, and source terminals coupled to ground. Other types of memory cells can be utilized in other embodiments, including but not limited to many types of programmable resistance memory cells like phase change based memory cells, magnetoresistance based memory cells, metal oxide based memory cells, and others.

FIG. 2 illustrates an alternative embodiment, in which components corresponding to components of FIG. 1 have like reference numerals and are not described again. In the embodiment of FIG. 2, the memory cells in the array 20 are coupled between corresponding bit lines and a common source line 21. The common source line 21 is coupled to a source bias control circuit 22, which is also connected to the bit line circuits 12. The source bias control circuit 22 provides a feedback signal on line 23 to the bit line circuits based on variations in the voltage on the common source line 21. The bit line circuits 12 can adjust the level of bias voltages applied to the bit lines by the bit line circuits 12 in response to the feedback signal on line 23. This can be used to compensate for a source crowding effect. If the source voltage on the common source line increases, a corresponding increase in the bit line bias voltages can be induced.

FIG. 3 illustrates an in-memory sum-of-products circuit including an expanded array of memory cells, such as NOR flash memory cells. The expanded array includes a plurality of blocks (e.g. 50, 51) of memory cells. In this example, the array includes 512 word lines WL0 to WL511, where each block of memory cells includes 32 rows. Thus, block 50 includes memory cells on word lines WL0 to WL31, and block 51 includes memory cells on word lines WL480 to WL511. Also, in this example, the array includes 512 bit lines BL0 to BL511.

Each block includes corresponding local bit lines that are coupled to the global bit lines BL0 to BL511 by corresponding block select transistors (e.g. 58, 59, 60, and 61) on block select lines BLT0 to BLT15.

A row decoder 55 (labeled XDEC) is coupled to the word lines, and is responsive to addressing or sequencing circuitry to select one or more word lines at a time in one or more blocks at a time as suits a particular operation. Also, the row decoder 55 includes word line drivers to apply word line voltages in support of the sum-of-products operation.

Each particular word line WLn is coupled to a row of memory cells in the array. The illustrated example, WLn is coupled to memory cells (e.g. 68, 69, 70, and 71). Each memory cell in the row corresponding to WLn is programmed with an analog or multibit value W_(i,n), where the index i corresponds to the bit line or column in the array, and the index n corresponds to the word line or row in the array.

Each bit line is coupled to bit line bias circuits, including a corresponding bit line clamp transistor (75, 76, 77, and 78). The gate of each bit line clamp transistor is coupled to a corresponding digital-to-analog converter DAC (80, 81, 82, and 83). Each digital-to-analog converter has a digital input corresponding to the input variable X_(1,n), where the index i corresponds with the bit line number and the index n corresponds with the selected word line number. Thus, the input value on the digital-to-analog converter DAC 80 on bit line BL0 receives a digital input X_(0,n) during the sum-of-products computation for the row corresponding to word line WLn. In other embodiments, the input variables can be applied by varying the block select line voltages connected to the block select transistors (e.g. 58, 59, 60, and 61) on block select lines BLT0 to BLT15. In this embodiment, the block select transistors are part of the bit line bias circuits.

In the illustrated example, the array includes a set of bit lines BL0 to BL511 which is arranged in 128 subsets of four bit lines each. The four bit lines for each subset are coupled through the corresponding bit line clamp transistors to a summing node (e.g. 85, 86), which is in turn coupled to a corresponding current sensing sense amplifier SA0 (90) and SA127 (91). The outputs of the sense amplifiers on lines 92, 93 are digital values representing the sum of the terms represented by the cells on the corresponding four bit lines on word line WLn. These digital values can be provided to a digital summing circuit to produce an output representing a 512 term sum-of-products computation, based on in-memory computation of 128 four-term sum-of-products computations.

In other embodiments, the number of bit lines in each subset can be any number, up to and including all of the bit lines in the set of bit lines in the array. The number of bit lines in each subset can be limited based on the range of the sense amplifiers utilized. The range of the sense amplifiers is a trade-off between a variety of factors including the complexity of the circuitry required, and the speed of operation required for a given implementation.

As mentioned above, each memory cell is programmed with a weight value W_(i,n). In an example in which the memory cell is a flash cell, the weight value can be represented by a threshold voltage that is programmed by charge tunneling into the charge trapping structure of the cell. Multilevel programming or analog programming algorithms can be utilized, in which the power applied for the purposes of programming a value in the memory cell is adjusted according to the desired threshold voltage.

FIG. 4 illustrates a representative distribution of threshold voltages usable to store four different weight values in each cell. For example, the weight stored in a given cell can have a first value falling within the distribution 100 programmed to have a minimum threshold of 2.5 V, a second value falling within the distribution 101 programmed to have a minimum threshold of 3.5 V, a third value falling within distribution 102 programmed to have a minimum threshold of 4.5 V and a fourth value falling within distribution 103 program to have a minimum threshold of 5.5 V. In order to execute a sum-of-products operation for memory cells having weights within these ranges of thresholds, a word line voltage 104 of about 6.5 V can be applied. The current output of a memory cell receiving the word line voltage will be a function of the difference between the word line voltage and the threshold value stored in the cell, and the bit line bias voltage applied to the line by the bias voltage applied by the bit line circuits.

In some embodiments, the threshold voltages achieved during the programming operation can be implemented using an analog technique, which does not rely on minimum or maximum threshold levels for each programming operation, but rather relies on the power applied in one pulse or multiple pulses during the programming operation which might be determined based on analog or digital inputs.

FIG. 5 illustrates an example of a digital-to-analog converter which accepts a three-bit input value (X_(0,n)) stored in a register 150. The output of the register 150 is coupled to a multiplexer 151, and selects one of the inputs to the multiplexer. For a three-bit input value, the multiplexer selects from among eight inputs. The inputs Q1 to Q8 in this example are generated by a resistor ladder 152. The resistor ladder 152 includes a current source implemented using an operational amplifier 153 having output driving the gate of a p-channel transistor 154. The source of the p-channel transistor 154 is coupled to the resistor ladder 152. The operational amplifier 153 has a first input coupled to a bandgap reference voltage BGREF which can be about 0.8 V for example, and a second input connected in feedback 155 to the source of the p-channel transistor 154. The output of the multiplexer 151 is coupled to an operational amplifier in a unity gain configuration, with an output connected to the gate of n-channel transistor 161, which has its source connected via resistor 162 to ground, and in feedback 163 to the second input of the operational amplifier 160.

The bit line circuits on each of the bit lines in an embodiment like that of FIG. 3 can have corresponding three-bit registers (e.g. 150) coupled to three-bit digital-to-analog converters. Of course converters of greater or lesser precision can be utilized as suits a particular implementation.

FIG. 6 illustrates an example of a sense amplifier in a circuit like that of FIG. 3. For example, a sense amplifier like that of FIG. 6 can be configured to sense currents over a range of about 4 μA to about 128 μA, and convert those values into a three-bit digital output Bit0, Bit1, Bit2.

In this diagram, the current ISENSE from an input summing node corresponding to the outputs from a subset of the bit lines in the array is represented by the current ISENSE 200. The current ISENSE 200 is coupled to a current sensing circuit having an input side including transistor set 210, 211, and a reference side including transistor set 212, 213.

The input side transistor set 210, 211 includes transistors MSB[2:0] 210 which have inputs connected to corresponding enable signals EN[2:0] which are asserted during a sensing sequence as described below. Also, the input side transistor set 210, 211 includes transistors MPB[2:0] 211 configured in series with corresponding transistors in the transistor set MSB[2:0] 210.

Reference side transistor set 212, 213 includes transistors MSA[2:0] 212 which have inputs connected to corresponding enable signals EN[2:0] which are asserted during a sensing sequence as described below. Also, the reference side transistor set 212, 213 includes current mirror reference transistors MPA[2:0] configured in series with corresponding transistors in the transistor set MSA[2:0]. The gates of the transistors MPA[2:0] are connected to the sources of the transistors, and in a current mirror configuration with the gates of the transistors MPB[2:0].

A reference current I-ref is applied to the reference side transistor set, and is generated using a reference current generator 220. The reference current generator 220 includes current source transistors 225, 226, 227 having their gates controlled by a reference voltage VREF. The current source transistors 225, 226, 227 are sized so as to produce respective currents 16 μA, 32 μA and 64 μA.

The outputs of the current source transistors 225, 226, 227 are connected to corresponding enable transistors 221, 222, 223, which are controlled respectively by control signals EN0, EN1 and EN2, which also control the transistors MSA[2:0] 212 and MSB[2:0] 210. The enable transistors 221, 222, 223 connect the current source transistors to the node 215, at which the current I-ref is provided.

The sense amplifier includes a sensing node 201, which fluctuates according to the difference between the current ISENSE 200 and the reference current I-ref, as adjusted by scaling of the current mirror transistors on the input side relative to the reference side. The sensing node 201 is connected to the D input of three latches 230, 231, 232. The latches 230, 231, 232 are clocked by the signals on the outputs of corresponding AND gates 240, 241, 242. The AND gates 240, 241, 242 receive as inputs the control signals sense2, sense1, sense0 respectively and a sensing clock signal clk. The outputs of the latches 230, 231, 232 provide the three bit output Bit0, Bit1, Bit2 of the sense amplifier. The outputs Bit1 and Bit2, where Bit2 is the most significant bit, are coupled to the control logic 235, which generates the control signals EN[2:0].

FIG. 7 illustrates a timing diagram for the circuit of FIG. 6. As can be seen, the control signals Sense0 to Sense2 are asserted in sequence. Upon assertion of the control signal Sense0, the enable signal EN2 is asserted. In this case, the reference current I-ref will be equal to the current through transistor 227 or 64 μA. The MSB latch 232 will store a bit indicating whether the current is above or below 64 μA.

Upon assertion of the control signal Sense1, both control signal EN2 and control signal EN1 are asserted if Bit2 is 1, corresponding to the value above 64 μA, and the control signal EN1 is not asserted if the Bit2 is zero. In the first case, this results in producing a current I-ref equal to the sum-of-currents from transistors 226 and 227, or 96 μA, in this example. In the second case, this results in producing a current I-ref equal to the current from transistor 226 alone, or 32 μA, in this example. The latch 231 will store a value Bit1 indicating whether the current is above or below 96 μA in the first case, or above or below 32 μA in the second case.

Upon assertion of the control signal Sense2, in the first case, all three control signals EN2, EN1 and EN0 are asserted in the case, illustrated resulting in a current I-ref equal to 112 μA, if both Bit2 and Bit1 are 1. If Bit1 is 0 (case Data=(1,0,x) not shown), then the control signal EN1 is not asserted resulting in a current I-ref equal to 80 μA.

Upon assertion of control signal Sense2 in the second case, only the control signal EN0 is asserted, resulting in a current I-ref equal to 16 μA if both Bit2 and Bit1 are zero. If Bit1 is 1 (case Data=(0,1,x) not shown), then both EN1 and EN0 are asserted, resulting in a current I-ref equal to 48 μA.

The table shown in FIG. 8 illustrates the logic, which can be executed by the control circuitry illustrated in FIG. 1 for example.

FIG. 9 is a flowchart showing a method for in-memory sum-of-product computation utilizing a memory array including a plurality of bit lines and a plurality of word lines, such as a NOR flash array.

The illustrated method includes for each row being utilized in a sum-of-products operation, programming a number P sets of memory cells in a row of the array, with M memory cells in each set, the P sets of memory cells on word line WLn and on bit lines BLi, for i going from 0 to P*M−1, with the values W_(i,n), for i going from 0 to P*M−1 (300). Also, the method includes biasing the bit lines BLi, with values X_(i,n), respectively, for i going from 0 to P*M−1 (301). To cause execution of a sum-of-products computation, the method includes applying a word line voltage to word line WLn so that the memory cells on the row conduct current corresponding to a product from respective cells in the row of W_(i,n)*X_(i,n)(302). While applying the word line voltage, the method includes summing the currents on the M bit lines connected to each of the P sets of memory cells, to produce P output currents (303). An output of the sum-of-products operation is produced by sensing the P output currents (304).

The flowchart in FIG. 9 illustrates logic executed by a memory controller or by in-memory sum-of-products device. The logic can be implemented using processors programmed using computer programs stored in memory accessible to the computer systems and executable by the processors, by dedicated logic hardware, including field programmable integrated circuits, and by combinations of dedicated logic hardware and computer programs. It will be appreciated that many of the steps can be combined, performed in parallel, or performed in a different sequence, without affecting the functions achieved. In some cases, as the reader will appreciate, a rearrangement of steps will achieve the same results only if certain other changes are made as well. In other cases, as the reader will appreciate, a rearrangement of steps will achieve the same results only if certain conditions are satisfied. Furthermore, it will be appreciated that the flow chart shows only steps that are pertinent to an understanding of the technology presented, and it will be understood that numerous additional steps for accomplishing other functions can be performed before, after and between those shown.

FIG. 10 illustrates an in-memory sum-of-products circuit including an expanded array of memory cells, such as NOR flash memory cells, configurable for applying input values on a plurality of word lines, and weights on bit line bias circuits, operable to sum the current from a plurality of cells on one bit line at a time. The expanded array includes a plurality of blocks (e.g. 550, 551) of memory cells. In this example, the array includes 512 word lines WL0 to WL511, where each block of memory cells includes 32 rows. Thus, block 550 includes memory cells on word lines WL0 to WL31, and block 551 includes memory cells on word lines WL480 to WL511. Also, in this example, the array includes 512 bit lines BL0 to BL511.

Each block includes corresponding local bit lines that are coupled to the global bit lines BL0 to BL511 by corresponding block select transistors (e.g. 558, 559, 560, and 561) on block select lines BLT0 to BLT15.

A row decoder 555 (labeled XDEC) is coupled to the word lines, and is responsive to addressing or sequencing circuitry to select a plurality of word lines at a time in one or more blocks at a time as suits a particular operation. Also, the row decoder 555 includes word line drivers to apply word line voltages in support of the sum-of-products operation.

Each particular word line WLn is coupled to a row of memory cells in the array. The illustrated example, WLn is coupled to memory cells (e.g. 568, 569, 570, and 571). Each memory cell in the row corresponding to WLn is programmed with an analog or multibit value W_(i,n), where the index i corresponds to the bit line or column in the array, and the index n corresponds to the word line or row in the array.

Each bit line is coupled to bit line bias circuits, including a corresponding bit line clamp transistor (565,566, 567, and 568). The gate of each bit line clamp transistor is coupled to a corresponding digital-to-analog converter DAC (580, 581, 582, and 583). Each digital-to-analog converter has a digital input corresponding to the input variable X_(i,n), where the index i corresponds with the bit line number and the index n corresponds with the selected word line number. Thus, the input value on the digital-to-analog converter DAC 580 on bit line BL0 receives a digital input X_(0,n) during the sum-of-products computation for the row corresponding to word line WLn. In other embodiments, the input variables can be applied by varying the block select line voltages connected to the block select transistors (e.g. 558, 559, 560, and 561) on block select lines BLT0 to BLT15. In this embodiment, the block select transistors are part of the bit line bias circuits.

In the illustrated example, the array includes a set of bit lines BL0 to BL511 which is arranged in 128 subsets of four bit lines each. The four bit lines for each subset are coupled through the corresponding bit line clamp transistors to a switch (e.g. 585, 586), operable to select one bit line from the corresponding subset, and connect the selected bit line to a corresponding current sensing sense amplifier SA0 (590) and SA127 (591). The outputs of the sense amplifiers on lines 592, 593 are digital values representing the sum of the terms represented current in a plurality of cells on one selected bit line. These digital values can be provided to a digital summing circuit to produce an output representing a sum-of-products computation, based on in-memory computation of 128 sum-of-products computations. The switches can be operated to switch in sequence from bit line to bit line, to produce a sequence of digital outputs representing the sum of current on corresponding bit lines. In other embodiments, a sense amplifier can be connected to each bit line, and the switches 585, 586 may be eliminated.

In other embodiments, the number of bit lines in each subset can be any number, up to and including all of the bit lines in the set of bit lines in the array. The number of bit lines in each subset can be limited based on the range of the sense amplifiers utilized. The range of the sense amplifiers is a trade-off between a variety of factors including the complexity of the circuitry required, and the speed of operation required for a given implementation.

As mentioned above, each memory cell is programmed with a weight value W_(i,n). In an example in which the memory cell is a flash cell, the weight value can be represented by a threshold voltage that is programmed by charge tunneling into the charge trapping structure of the cell. Multilevel programming or analog programming algorithms can be utilized, in which the power applied for the purposes of programming a value in the memory cell is adjusted according to the desired threshold voltage.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. 

What is claimed is:
 1. A method for performing an in-memory multiply-and-accumulate function, using an array of memory cells, comprising: applying a word line voltage to word line WLn to access M memory cells in a row of the array on bit lines BLi, for i going from 0 to M-1, the M memory cells storing values W_(i,n), for i going from 0 to M-1; biasing bit lines BLi, with input values X_(i,n), respectively, for i going from 0 to M-1, so that individual ones of the M memory cells on word line WLn conduct current indicative of product of W_(i,n) and X_(i,n), for i going from 0 to M-1, wherein biasing the bit lines BLi includes (i) converting, using corresponding digital-to-analog converters, digital inputs Xi,n to analog bias voltages and (ii) applying the analog bias voltages to corresponding bit line clamp transistors to generate corresponding bit line voltages as a function of the digital inputs Xi,n for the respective bit lines BLi; summing the currents from a plurality of memory cells to produce an output current; and sensing the output current.
 2. The method of claim 1, wherein summing the currents from the plurality of memory cells includes summing the currents on the bit lines BLi, for i going from 0 to M-1.
 3. The method of claim 1, wherein summing the currents from the plurality of memory cells includes applying word line voltage to a plurality of word lines in parallel so that the current on one of the bit lines BLi is the output current including currents from the plurality of memory cells.
 4. The method of claim 1, wherein the memory cells comprise multilevel non-volatile memory cells.
 5. The method of claim 1, including: applying a word line voltage to word line WLn to access a number P sets of memory cells in a row of the array, with M memory cells in each set, the P sets of memory cells on word line WLn and on bit lines BLi, for i going from 0 to P*M−1, storing values W_(i,n), for i going from 0 to P*M−1, one of said P sets including said first mentioned M memory cells; biasing the bit lines BLi, with values X_(i,n), respectively, for i going from 0 to P*M−1, so that the memory cells on the row of the array conduct current corresponding to a product from respective memory cells in the row of W_(i,n)*X_(i,n); summing the currents on the M bit lines connected to each of the P sets of memory cells, to produce P output currents; and sensing the P output currents.
 6. The method of claim 1, including programming the memory cells on the row with the weights W_(i,n).
 7. The method of claim 1, including adjusting the biasing on the bit lines BLi, for i going from 0 to M-1, in response to variations in voltage on a source line coupled to at least part of the array of memory cells.
 8. An in-memory multiply-and-accumulate circuit, comprising: a memory array including memory cells on a set of word lines and a set of bit lines; a row decoder coupled to the set of word lines, configured to apply word line voltages to one or more selected word lines in the set; a plurality of bit line bias circuits, individual ones of the bit line bias circuits in the plurality of bit line bias circuits having corresponding inputs connected to an input data path, and having outputs connected to respective bit lines in the set of bit lines, and producing bit line bias voltages for the respective bit lines as a function of input values on the corresponding inputs; a plurality of current sensing circuits, each of the plurality of current sensing circuits being connected to receive currents from one or more bit lines in the set of bit lines, and to produce an output in response to a sum-of-the-currents from a corresponding plurality of memory cells; and circuits to program a first memory cell in the array with a weight W, wherein a first bit line bias circuit of the plurality of bit line bias circuits includes (i) a digital-to-analog converter to convert a multiple-bit digital input X to an analog bias voltage, and (ii) a transistor to receive the analog bias voltage at a gate of the transistor and to generate a bit line voltage that is output to a first bit line corresponding to the first memory cell, and wherein the first memory cell is to conduct a current indicative of a product of the weight W and the input X.
 9. The circuit of claim 8, wherein multi-member subsets of the set of bit lines are connected to a current summing node, and current sensing circuits in the plurality of current sensing circuits are connected to respective summing nodes.
 10. The circuit of claim 8, wherein current sensing circuits in the plurality of current sensing circuits are configured to sense current from one of the bit lines in the set of bit lines, while the row decoder applies word line voltages to a plurality of word lines in parallel so that the current on one of the bit lines includes currents from the plurality of memory cells.
 11. The circuit of claim 8, wherein the individual ones of the bit line bias circuits in the plurality of bit line bias circuits comprise digital-to-analog converters.
 12. The circuit of claim 8, including circuits to program the memory cells in the array with weights W_(i,n), in memory cells in a row of the array on word line WLn in the set of word lines and on bit lines BLi in the set of bit lines to store values.
 13. The circuit of claim 8, wherein the memory cells comprise multilevel non-volatile memory cells.
 14. The circuit of claim 8, wherein the plurality of bit line bias circuits include digital-to-analog converters to convert multiple-bit digital inputs X_(i,n) to analog bias voltages, and to apply the analog bias voltages to the respective bit lines BLi.
 15. The circuit of claim 8, wherein the memory array has a NOR architecture.
 16. The circuit of claim 15, wherein the memory array comprises dielectric charge trapping memory cells.
 17. The circuit of claim 8, wherein the plurality of bit lines are configured in P sets of bit lines having M members each, where M is greater than one, and the plurality of sensing circuits are connected to corresponding sets in the P sets of bit lines.
 18. The circuit of claim 8, wherein the memory array of memory cells comprises charge trapping memory cells in a NOR architecture having a source line coupled to at least some of the memory cells in the array, and including a source line bias circuit coupled to the plurality of bit line bias circuits, to provide feedback in response to variations in voltage on the source line.
 19. The circuit of claim 15, wherein the memory array comprises floating gate memory cells.
 20. An in-memory multiply-and-accumulate circuit, comprising: a memory array including a first memory cell on a first word line and a first bit line; a row decoder coupled to a set of word lines that includes the first word line, configured to apply word line voltages to one or more selected word lines in the set; a first bit line bias circuit comprising (i) a digital-to-analog converter to receive a corresponding first input X and to generate an analog signal, and (ii) a bit line clamp transistor to receive the analog signal at a gate of the bit line clamp transistor, and to generate an output connected to the first bit line, the first bit line bias circuit to produce a first bit line bias voltage for the first bit line as a function of the first input X; and circuits to program the first memory cell with a weight W, wherein the first memory cell is to conduct a current indicative of a product of the weight W and the input X. 